manakin
@manakin
This (mega) thread will follow my daily progress on “Digital Design & Computer Architecture: RISC-V Edition” by David & Sarah Harris
1 reply
0 recast
3 reactions
manakin
@manakin
Today I began Ch 3 on sequential circuits which differ from combinational circuits (covered in ch 2) as they have memory. Sequential logic compresses prior inputs into the system’s state.
1 reply
0 recast
0 reaction
manakin
@manakin
First covered a simple instance of sequential circuits called SR latches (two cross-coupled NOR gates) that experiences awkward behavior when R & S are asserted [Q & Ǭ = 0].
1 reply
0 recast
0 reaction
manakin
@manakin
The D latch solves this with two cross-coupled AND gates that limit state transitions to the cases when the SR latch produces non-awkward behavior (aka when Q ≠ Ǭ). Notice that when CLK (clock) = 0, the state doesn’t update and only depends on the previous state. When CLK = 1, D alone determines Q & Ǭ.
1 reply
0 recast
0 reaction
manakin
@manakin
27 SEP ’23 – Using two d latches controlled by 1 clock (CLK) can be used to build a D flip-flop. As will be explained in more detail in the next two casts, the D flip-flop copies D to Q on the rising edge of the clock (when CLK transitions from 0 to 1 aka rises) and remembers its last captured state (Q) otherwise.
1 reply
0 recast
0 reaction
manakin
@manakin
D flip-flop, cont.: Time T = 0, CLK = 0. As CLK flows through an inverter, the master’s (L1’s) D latch is permitted to update its state. D flows from the L1’s input to L1’s output, N1. As L2’s CLK = 0, its state is barred from being updated. Next we will change CLK from 0 to 1 and update L2’s state.
1 reply
0 recast
0 reaction
manakin
@manakin
D flip-flop, cont.: Time T = 1, CLK = 1. L2 is permitted to update it’s state from its input, N1 and then Q is thus set to N1. So when CLK transitions from 0 to 1, the input D is copied to the output. At all other times, the previous state of Q is remembered as the path from D to Q is blocked.
1 reply
0 recast
0 reaction
manakin
@manakin
You can conjoin N flip-flops together with a common CLK to create an N-bit register that passes N bits simultaneously from D_0 through D_3 onto Q_0 onto Q_3. Registers are important components of most sequential circuits.
1 reply
0 recast
0 reaction
