This (mega) thread will follow my daily progress on “Digital Design & Computer Architecture: RISC-V Edition” by David & Sarah Harris

Today I began Ch 3 on sequential circuits which differ from combinational circuits (covered in ch 2) as they have memory. Sequential logic compresses prior inputs into the system’s state.

First covered a simple instance of sequential circuits called SR latches (two cross-coupled NOR gates) that experiences awkward behavior when R & S are asserted [Q & Ǭ = 0].

The D latch solves this with two cross-coupled AND gates that limit state transitions to the cases when the SR latch produces non-awkward behavior (aka when Q ≠ Ǭ). Notice that when CLK (clock) = 0, the state doesn’t update and only depends on the previous state. When CLK = 1, D alone determines Q & Ǭ.

27 SEP ’23 – Using two d latches controlled by 1 clock (CLK) can be used to build a D flip-flop. As will be explained in more detail in the next two casts, the D flip-flop copies D to Q on the rising edge of the clock (when CLK transitions from 0 to 1 aka rises) and remembers its last captured state (Q) otherwise.

D flip-flop, cont.: Time T = 0, CLK = 0. As CLK flows through an inverter, the master’s (L1’s) D latch is permitted to update its state. D flows from the L1’s input to L1’s output, N1. As L2’s CLK = 0, its state is barred from being updated. Next we will change CLK from 0 to 1 and update L2’s state.

D flip-flop, cont.: Time T = 1, CLK = 1. L2 is permitted to update it’s state from its input, N1 and then Q is thus set to N1. So when CLK transitions from 0 to 1, the input D is copied to the output. At all other times, the previous state of Q is remembered as the path from D to Q is blocked.

You can conjoin N flip-flops together with a common CLK to create an N-bit register that passes N bits simultaneously from D_0 through D_3 onto Q_0 onto Q_3. Registers are important components of most sequential circuits.

Enabled flip-flops use a CLK and ENABLE signal (passed through an AND-gate), to gate state transitions with more flexibility. This provides selective operation, allowing updates only when ENABLE is active. Performing logic on a clock can easily cause glitches so the authors recommend using this tool carefully.

Similar to enabled flip-flops, synchronously-resettable flip-flops are a sequential circuit that adds another input, RESET, to gate a specific state transition (when to reset Q to zero). When RESET is FALSE, the circuit behaves like a D flip-flop but when RESET is TRUE, the output (Q) is reset to zero.

28 Sep ’23 – Here is an example of the potential inputs of CLK & D and how they would affect the outputs of Q for each of a D latch and a D flip-flop. Notice that the D flip-flop updates its state on each rising edge of CLK (Q’s default = 0 so only causes one change) and Q (latch) mirrors D assuming CLK = 1.

In the below async (async because the output feeds back into an input) sequential circuit, that’s also a D latch, provides an example of a race condition in which when D = CLK = 1 in the first time step and then CLK falls to 1, the output changes based on a race from the changes to propagate throughout the circuit.